Samsung Foundry: 4nm manufacturing uses EUV and Gate all Around

Samsung has revealed first details on upcoming manufacturing steps. The plan is for manufacturing processes for 8 nm, 7 nm, 6 nm, 5 nm and 4 nm, which Samsung will offer in the coming years. In addition, unused gate all-around technologies are used.

On the Samsung Foundry Forum, the Korean electronics giant has announced details of the future production steps and announced steps ahead. In the first place, it is surprising that almost every digit of 10 nm is used downwards, although it was previously planned to address the 7 nm and 5 nm process as the most important solutions for the future. But behind the intermediate steps the core is often the same, but with appropriate optimizations. Nuclear processes will be the new plans after 7 and 4 nm.

8 nm still without, 7 nm with EUV

The 10-nm-process (10LPP) is therefore behind 8LPP (8nm LowPowerPlus), into which some optimizations flow and thus the packing density and also power 10LPP slightly increase. According to Samsung, the last step before EUV lithography is used.

This EUV lithography is to be used at 7 nm (7LPP) and thus mark a milestone for the future. However, as with all other semiconductor manufacturers, it is expected that only a few partial steps under EUV will be exposed at the outset, while classical lithography will continue to be used in other segments – TSMC also does so at 7 nm. Because Samsung speaks of the use of a 250 watt strong EUV light source of ASML, but this is not even developed yet let alone. Current systems work with 80 to 125 watts, but ASML focuses on the research and development of stronger light sources.

Intermediate steps with 6 and 5 nm at Samsung

Contrary to previous data, 5 nm (5LPP) is not a really new process, but an intermediate solution – just like 6LPP. At 6 nm, Samsung is talking about optimizing the performance and power consumption of the 7 nm process. For Samsung 5LPP, Samsung is talking about quite similar improvements, but with the addition of the new technologies that are used in the 4LPP series.

4LPP uses Gate All Around FET for the first time

The next generation of FinFETs manufacturing technology is a challenge for all semiconductor manufacturers. The use of “gate all around” is one of the solutions that has been researched and considered for many years and now seems to be establishing itself as a solid solution for the near future.

The base is very similar to FinFET, but instead of “only” from three sides, the name of the name is supposed to completely surround the nanowires, thus enabling the “perfect transistor”. Samsung also calls a part of the technology also MBCFETTM (Multibridge Channel FET), which will show the differences, the exact advantages, and characteristics, the coming years. According to the Chinese media, the risk production will begin in 2020 at the earliest, and by the year 2021, it is difficult to expect a serial production.

Also FD-SOI in 18 nm in the program

Also against Globalfoundries own FD-SOI program Samsung has a counterpart in planning. But while Globalfoundries is at 22 and 12 nm – which is so at least in the marketing language so calls – Samsung will only offer an 18-nm FD-SOI process. How exactly it is ordered about its properties, was not given, also here at the earliest 2021 the serial production will be available.

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